To increase an operating speed of an integrated circuit device such as a microprocessor and a memory, it is necessary to reduce a parasitic capacitance between a gate electrode and a source/drain electrode of a transistor. Furthermore, to reduce power consumption, it is necessary to reduce a leakage current. In a case where a bias applied to the gate electrode is different from a bias applied to the source/drain electrode, an electric field concentrates at ends of the gate electrode, and the leakage current occurs. To reduce the leakage current, it is necessary to relax the electric field at the end of the gate electrode.
In a FD-accumulation-type solid-state imaging device in which charges generated by a photoelectric conversion element are accumulated in a FD diffusion layer as using one of source/drain electrodes of a pixel transistor as the FD diffusion layer, low leakage is required for the FD diffusion layer. However, due to a potential difference between the gate electrodes of the transfer transistor and the reset transistor and the FD diffusion layer, electric field concentration occurs at the end of the gate electrode, and the leakage current occurs. Furthermore, in a case where a high photoelectric conversion efficiency is required, reduction in a parasitic capacitance between the gate electrode and the FD diffusion layer is required.
Therefore, Patent Document 1 discloses a technology for suppressing hot carriers and reducing the parasitic capacitance by adjusting a layout between the gate electrodes. That is, two transistors are arranged adjacent to each other, and an interval between the two gate electrodes is set to be narrow. With this structure, a width of a sidewall between the gate electrodes is narrower than a width of a sidewall formed on a side wall of a gate electrode in an isolated pattern. Therefore, a width of the sidewall on the side of a source electrode can be narrowed, and a width of the sidewall on the side of a drain electrode can be widened. By using a diffusion layer region between the gate electrodes as the source electrode, only a series resistance between the gate electrode and the source electrode is reduced, and an overlap between the gate electrode and the drain electrode is reduced. Accordingly, it is possible to suppress the generation of the hot carriers on the drain electrode side and reduce the parasitic capacitance.
Furthermore, in Patent Document 2, a structure is proposed in which a height of the gate electrode of the transfer transistor on the FD diffusion layer side is set higher than that on the photodiode side. With this structure, a width of the sidewall formed on the side surface of the gate electrode is wider only on the side having contact with the FD diffusion layer. For example, in a case of an electron-accumulation-type solid-state imaging device, N-type ions are implanted into the FD diffusion layer by self-alignment relative to the sidewall. As a result, while maintaining transfer characteristics from the photodiode, it is possible to reduce the parasitic capacitance with the FD diffusion layer and reduce the leakage current by relaxing the electric field at the end of the gate electrode of the transfer transistor.